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1 lt1809/lt1810 the lt ? 1809/lt1810 are single/dual low distortion rail- to-rail input and output op amps with a 350v/ m s slew rate. these amplifiers have a C3db bandwidth of 320mhz at unity-gain, a gain-bandwidth product of 180mhz (a v 3 10) and an 85ma output current to fit the needs of low voltage, high performance signal conditioning systems. the lt1809/lt1810 have an input range that includes both supply rails and an output that swings within 20mv of either supply rail to maximize the signal dynamic range in low supply applications. the lt1809/lt1810 have very low distortion (C90dbc) up to 5mhz that allows them to be used in high performance data acquisition systems. the lt1809/lt1810 maintain their performance for sup- plies from 2.5v to 12.6v and are specified at 3v, 5v and 5v supplies. the inputs can be driven beyond the sup- plies without damage or phase reversal of the output. the lt1809 is available in the 8-pin so package with the standard op amp pinout and the 6-pin sot-23 package. the lt1810 features the standard dual op amp pinout and is available in 8-pin so and msop packages. these devices can be used as a plug-in replacement for many op amps to improve input/output range and performance. n driving a/d converters n low voltage signal processing n active filters n rail-to-rail buffer amplifiers n video line driver , ltc and lt are registered trademarks of linear technology corporation. n C3db bandwidth: 320mhz, a v = 1 n gain-bandwidth product: 180mhz, a v 3 10 n slew rate: 350v/ m s n wide supply range: 2.5v to 12.6v n large output current: 85ma n low distortion, 5mhz: C 90dbc n input common mode range includes both rails n output swings rail-to-rail n input offset voltage, rail-to-rail: 2.5mv max n common mode rejection: 89db typ n power supply rejection: 87db typ n open-loop gain: 100v/mv typ n shutdown pin: lt1809 n single in 8-pin so and 6-pin sot-23 packages n dual in 8-pin so and msop packages n operating temperature range: C 40 c to 85 c single/dual 180mhz, 350v/ m s rail-to-rail input and output low distortion op amps high speed adc driver distortion vs frequency features descriptio u applicatio s u typical applicatio u + lt1809 ltc 1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps ?v ?v r2 1k r1 1k v in 1v p-p c1 470pf ? in 1809 ta01 +a in r3 49.9 frequency (mhz) 0.3 ?0 distortion (db) ?0 ?0 ?0 11030 1809 ta02 ?0 ?0 ?00 ?10 a v = +1 v in = 2v p-p v s = 5v r l = 100 , 2nd r l = 1k, 3rd r l = 1k, 2nd r l = 100 , 3rd
2 lt1809/lt1810 total supply voltage (v + to v C ) ........................... 12.6v input voltage (note 2) .............................................. v s input current (note 2) ........................................ 10ma output short-circuit duration (note 3) ............ indefinite operating temperature range (note 4) .. C 40 c to 85 c (note 1) 1 2 3 4 8 7 6 5 top view nc v + out nc shdn ?n +in v s8 package 8-lead plastic so + order part number s6 part marking ltky ltuf lt1809cs6 lt1809is6 t jmax = 150 c, q ja = 100 c/w (note 9) absolute axi u rati gs w ww u package/order i for atio uu w specified temperature range (note 5) ... C 40 c to 85 c junction temperature ........................................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number s8 part marking 1809 1809i lt1809cs8 LT1809IS8 out 1 v 2 +in 3 6 v + 5 shdn 4 in top view s6 package 6-lead plastic sot-23 t jmax = 150 c, q ja = 145 c/w (note 9) order part number ms8 part marking ltrf lttq lt1810cms8 lt1810ims8 order part number s8 part marking 1810 1810i lt1810cs8 lt1810is8 1 2 3 4 out a ?n a +in a v 8 7 6 5 v + out b ?n b +in b top view ms8 package 8-lead plastic msop t jmax = 150 c, q ja = 130 c/w (note 9) top view v + out b ?n b +in b out a ?n a +in a v s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 a b t jmax = 150 c, q ja = 100 c/w (note 9) t a = 25 c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 0.6 2.5 mv v cm = v C lt1809 so-8 0.6 2.5 mv v cm = v + 0.6 3.0 mv v cm = v C 0.6 3.0 mv d v os input offset shift v cm = v C to v + lt1809 so-8 0.3 2.0 mv v cm = v C to v + 0.3 2.5 mv input offset voltage match (channel-to-channel) (note 10) 0.7 6 mv i b input bias current v cm = v + 1.8 8 m a v cm = v C + 0.2v C 27.5 C13 m a d i b input bias current shift v cm = v C + 0.2v to v + 14.8 35.5 m a input bias current match (channel-to-channel) (note 10) v cm = v + 0.1 4 m a v cm = v C + 0.2v 0.2 8 m a consult factory for parts specified with wider operating temperature ranges.
3 lt1809/lt1810 t a = 25 c. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. symbol parameter conditions min typ max units i os input offset current v cm = v + 0.05 1.2 m a v cm = v C + 0.2v 0.2 4 m a d i os input offset current shift v cm = v C + 0.2v to v + 0.25 5.2 m a e n input noise voltage density f = 10khz 16 nv/ ? hz i n input noise current density f = 10khz 5 pa/ ? hz c in input capacitance 2pf a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 25 80 v/mv v s = 5v, v o = 1v to 4v, r l = 100 w to v s /2 4 10 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 15 42 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + 66 82 db v s = 3v, v cm = v C to v + 61 78 db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + 60 82 db v s = 3v, v cm = v C to v + 55 78 db input common mode range v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 71 87 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v 65 87 db minimum supply voltage (note 6) 2.3 2.5 v v ol output voltage swing low (note 7) no load 12 50 mv i sink = 5ma 50 120 mv i sink = 25ma 180 375 mv v oh output voltage swing high (note 7) no load 20 80 mv i source = 5ma 80 180 mv i source = 25ma 330 650 mv i sc short-circuit current v s = 5v 45 85 ma v s = 3v 35 70 ma i s supply current per amplifier 12.5 17 ma supply current, shutdown v s = 5v, v shdn = 0.3v 0.55 1.25 ma v s = 3v, v shdn = 0.3v 0.31 0.90 ma i shdn shdn pin current v s = 5v, v shdn = 0.3v 420 750 m a v s = 3v, v shdn = 0.3v 220 500 m a output leakage current, shutdown v shdn = 0.3v 0.1 75 m a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v s C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 2mhz 160 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v p-p 300 v/ m s fpbw full power bandwidth v s = 5v, v out = 4v p-p 23.5 mhz thd total harmonic distortion v s = 5v, a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C 86 db t s settling time 0.1%, v s = 5v, v step = 2v, a v = C 1, r l = 500 w 27 ns d g differential gain (ntsc) v s = 5v, a v = 2, r l = 150 w 0.015 % dq differential phase (ntsc) v s = 5v, a v = 2, r l = 150 w 0.05 deg electrical characteristics
4 lt1809/lt1810 symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 l 1 3.0 mv v cm = v C lt1809 so-8 l 1 3.0 mv v cm = v + l 1 3.5 mv v cm = v C l 1 3.5 mv v os tc input offset voltage drift (note 8) v cm = v + l 925 m v/ c v cm = v C l 925 m v/ c d v os input offset voltage shift v cm = v C to v + lt1809 so-8 l 0.5 2.5 mv v cm = v C to v + l 0.5 3.0 mv input offset voltage match (channel-to-channel) v cm = v C , v cm = v + l 1.2 6.5 mv (note 10) i b input bias current v cm = v + C 0.2v l 210 m a v cm = v C + 0.4v l C30 C14 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 16 40 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.1 5 m a (note 10) v cm = v C + 0.4v l 0.5 10 m a i os input offset current v cm = v + C 0.2v l 0.05 1.5 m a v cm = v C + 0.4v l 0.40 4.5 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.45 6 m a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 l 20 75 v/mv v s = 5v, v o = 1v to 4v, r l = 100 w to v s /2 l 3.5 8.5 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l 12 40 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + l 64 80 db v s = 3v, v cm = v C to v + l 60 75 db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C , v cm = v + l 58 80 db v s = 3v, v cm = v C , v cm = v + l 54 75 db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 70 83 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 64 83 db minimum supply voltage (note 6) l 2.3 2.5 v v ol output voltage swing low (note 7) no load l 12 60 mv i sink = 5ma l 55 140 mv i sink = 25ma l 200 400 mv v oh output voltage swing high (note 7) no load l 50 120 mv i source = 5ma l 110 220 mv i source = 25ma l 370 700 mv i sc short-circuit current v s = 5v l 40 75 ma v s = 3v l 30 65 ma i s supply current per amplifier l 15 20 ma supply current, shutdown v s = 5v, v shdn = 0.3v l 0.58 1.4 ma v s = 3v, v shdn = 0.3v l 0.35 1.1 ma i shdn shdn pin current v s = 5v, v shdn = 0.3v l 420 850 m a v s = 3v, v shdn = 0.3v l 220 550 m a output leakage current, shutdown v shdn = 0.3v l 2 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v s C 0.5 v the l denotes the specifications which apply over the 0 c t a 70 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. electrical characteristics
5 lt1809/lt1810 the l denotes the specifications which apply over the 0 c t a 70 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 145 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v p-p l 250 v/ m s fpbw full power bandwidth v s = 5v, v out = 4v p-p l 20 mhz symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 l 1 3.5 mv v cm = v C lt1809 so-8 l 1 3.5 mv v cm = v + l 1 4.0 mv v cm = v C l 1 4.0 mv v os tc input offset voltage drift (note 8) v cm = v + l 925 m v/ c v cm = v C l 925 m v/ c d v os input offset voltage shift v cm = v C to v + lt1809 so-8 l 0.5 3.0 mv v cm = v C l 0.5 3.5 mv input offset voltage match (channel-to-channel) v cm = v + , v cm = v C l 1.2 7 mv (note 10) i b input bias current v cm = v + C 0.2v l 212 m a v cm = v C + 0.4v l C35 C17 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 19 47 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.2 6 m a (note 10) v cm = v C + 0.4v l 0.6 12 m a i os input offset current v cm = v + C 0.2v l 0.08 2 m a v cm = v C + 0.4v l 0.5 6 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.58 7.5 m a a vol large-signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k to v s /2 l 17 60 v/mv v s = 5v, v o = 1v to 4v, r l = 100 w to v s /2 l 2.5 7 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k to v s /2 l 10 35 v/mv cmrr common mode rejection ratio v s = 5v, v cm = v C to v + l 63 80 db v s = 3v, v cm = v C to v + l 58 75 db cmrr match (channel-to-channel) (note 10) v s = 5v, v cm = v C to v + l 57 78 db v s = 3v, v cm = v C to v + l 52 72 db input common mode range l v C v + v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v l 69 83 db psrr match (channel-to-channel) (note 10) v s = 2.5v to 10v, v cm = 0v l 63 83 db minimum supply voltage (note 6) l 2.3 2.5 v v ol output voltage swing low (note 7) no load l 18 70 mv i sink = 5ma l 60 150 mv i sink = 25ma l 210 450 mv v oh output voltage swing high (note 7) no load l 55 130 mv i source = 5ma l 120 240 mv i source = 25ma l 375 750 mv i sc short-circuit current v s = 5v l 30 70 ma v s = 3v l 25 60 ma i s supply current per amplifier l 15 21 ma supply current, shutdown v s = 5v, v shdn = 0.3v l 0.58 1.5 ma v s = 3v, v shdn = 0.3v l 0.35 1.2 ma the l denotes the specifications which apply over the C 40 c t a 85 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5)
6 lt1809/lt1810 the l denotes the specifications which apply over the C 40 c t a 85 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v shdn = open; v cm = v out = half supply, unless otherwise noted. (note 5) electrical characteristics symbol parameter conditions min typ max units i shdn shdn pin current v s = 5v, v shdn = 0.3v l 420 900 m a v s = 3v, v shdn = 0.3v l 220 600 m a output leakage current, shutdown v shdn = 0.3v l 3 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v s C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 140 mhz sr slew rate v s = 5v, a v = -1, r l = 1k, v o = 4v p-p l 180 v/ m s fpbw full power bandwidth v s = 5v, v out = 4v p-p l 14 mhz t a = 25 c. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 0.8 3.0 mv v cm = v C lt1809 so-8 0.8 3.0 mv v cm = v + 0.8 3.5 mv v cm = v C 0.8 3.5 mv d v os input offset voltage shift v cm = v C to v + lt1809 so-8 0.35 2.5 mv v cm = v C to v + 0.35 3.0 mv input offset voltage match (channel-to-channel) v cm = v + , v cm = v C 16 mv (note 10) i b input bias current v cm = v + 210 m a v cm = v C + 0.2v C 30 C12.5 m a d i b input bias current shift v cm = v C + 0.2v to v + 14.5 40 m a input bias current match (channel-to-channel) v cm = v + 0.1 5 m a (note 10) v cm = v C + 0.2v 0.4 10 m a i os input offset current v cm = v + 0.05 2 m a v cm = v C + 0.2v 0.40 5 m a d i os input offset current shift v cm = v C + 0.2v to v + 0.45 7 m a e n input noise voltage density f = 10khz 16 nv/ ? hz i n input noise current density f = 10khz 5 pa/ ? hz c in input capacitance f = 100khz 2 pf a vol large-signal voltage gain v o = C 4v to 4v, r l = 1k 30 100 v/mv v o = C 2.5v to 2.5v, r l = 100 w 4.5 12 v/mv cmrr common mode rejection ratio v cm = v C to v + 70 89 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + 64 89 db input common mode range v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v 71 87 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v 65 90 db v ol output voltage swing low (note 7) no load 12 60 mv i sink = 5ma 50 140 mv i sink = 25ma 180 425 mv v oh output voltage swing high (note 7) no load 35 100 mv i source = 5ma 90 200 mv i source = 25ma 310 700 mv
7 lt1809/lt1810 electrical characteristics t a = 25 c. v s = 5v, v shdn = open, v cm = 0v, v out = 0, unless otherwise noted. symbol parameter conditions min typ max units i sc short-circuit current 55 85 ma i s supply current per amplifier 15 20 ma supply current, shutdown v shdn = 0.3v 0.6 1.3 ma i shdn shdn pin current v shdn = 0.3v 420 750 m a output leakage current, shutdown v shdn = 0.3v 0.1 75 m a v l shdn pin input voltage low 0.3 v v h shdn pin input voltage high v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 50 ns gbw gain-bandwidth product frequency = 2mhz 110 180 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, 175 350 v/ m s measured at v o = 3v fpbw full power bandwidth v out = 8v p-p 14 mhz thd total harmonic distortion a v = 1, r l = 1k, v o = 2v p-p , f c = 5mhz C 90 db t s settling time 0.1%, v step = 8v, a v = C 1, r l = 500 w 34 ns d g differential gain (ntsc) a v = 2, r l = 150 w 0.01 % dq differential phase (ntsc) a v = 2, r l = 150 w 0.01 deg symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 l 1 3.25 mv v cm = v C lt1809 so-8 l 1 3.25 mv v cm = v + l 1 3.75 mv v cm = v C l 1 3.75 mv v os tc input offset voltage drift (note 8) v cm = v + l 10 25 m v/ c v cm = v C l 10 25 m v/ c d v os input offset voltage shift v cm = v C to v + lt1809 so-8 l 0.5 2.75 mv v cm = v C to v + l 0.5 3.25 mv input offset voltage match (channel-to-channel) v cm = v C to v + l 1.2 6.5 mv (note 10) i b input bias current v cm = v + C 0.2v l 2.5 12.5 m a v cm = v C + 0.4v l C 37.5 C15 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 17.5 50 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.1 6 m a (note 10) v cm = v C + 0.4v l 0.5 12 m a i os input offset current v cm = v + C 0.2v l 0.06 2.25 m a v cm = v C + 0.4v l 0.5 6 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.56 8.25 m a a vol large-signal voltage gain v o = C 4v to 4v, r l = 1k l 27 80 v/mv v o = C 2.5v to 2.5v, r l = 100 w l 3.5 10 v/mv cmrr common mode rejection ratio v cm = v C to v + l 69 86 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 63 86 db input common mode range l v C v + v the l denotes the specifications which apply over the 0 c t a 70 c temperature range. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted.
8 lt1809/lt1810 the l denotes the specifications which apply over the 0 c t a 70 c temperature range. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. symbol parameter conditions min typ max units psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 70 83 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v l 64 83 db v ol output voltage swing low (note 7) no load l 20 80 mv i sink = 5ma l 50 160 mv i sink = 25ma l 210 475 mv v oh output voltage swing high (note 7) no load l 60 140 mv i source = 5ma l 120 240 mv i source = 25ma l 370 750 mv i sc short-circuit current l 45 75 ma i s supply current per amplifier l 17.5 25 ma supply current, shutdown v shdn = 0.3v l 0.6 1.5 ma i shdn shdn pin current v shdn = 0.3v l 420 850 m a output leakage current, shutdown v shdn = 0.3v l 3 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 85 170 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, l 140 300 v/ m s measured at v o = 3v fpbw full power bandwidth v out = 8v p-p l 12 mhz electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = v + lt1809 so-8 l 1 3.75 mv v cm = v C lt1809 so-8 l 1 3.75 mv v cm = v + l 1 4.25 mv v cm = v C l 1 4.25 mv v os tc input offset voltage drift (note 8) v cm = v + l 10 25 m v/ c v cm = v C l 10 25 m v/ c d v os input offset voltage shift v cm = v C to v + lt1809 so-8 l 0.5 3.00 mv v cm = v C to v + l 0.5 3.75 mv input offset voltage match (channel-to-channel) v cm = v C to v + l 1.2 7.5 mv (note 10) i b input bias current v cm = v + C 0.2v l 2.8 14 m a v cm = v C + 0.4v l C45 C17 m a d i b input bias current shift v cm = v C + 0.4v to v + C 0.2v l 19.8 59 m a input bias current match (channel-to-channel) v cm = v + C 0.2v l 0.1 7 m a (note 10) v cm = v C + 0.4v l 0.6 14 m a i os input offset current v cm = v + C 0.2v l 0.08 2.5 m a v cm = v C + 0.4v l 0.6 8 m a d i os input offset current shift v cm = v C + 0.4v to v + C 0.2v l 0.68 10.5 m a a vol large-signal voltage gain v o = C 4v to 4v, r l = 1k l 22 70 v/mv v o = C 2.5v to 2.5v, r l = 100 w l 310 v/mv the l denotes the specifications which apply over the C 40 c t a 85 c temperature range. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. (note 5)
9 lt1809/lt1810 note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. note 4: the lt1809c/lt1809i and lt1810c/lt1810i are guaranteed functional over the operating temperature range of C 40 c and 85 c. note 5: the lt1809c/lt1810c are guaranteed to meet specified performance from 0 c to 70 c. the lt1809c/lt1810c are designed, characterized and expected to meet specified performance from C 40 c to 85 c but are not tested or qa sampled at these temperatures. the lt1809i/lt1810i are guaranteed to meet specified performance from C40 c to 85 c. the l denotes the specifications which apply over the C 40 c t a 85 c temperature range. v s = 5v, v shdn = open, v cm = 0v, v out = 0v, unless otherwise noted. (note 5) note 6: minimum supply voltage is guaranteed by power supply rejection ratio test. note 7: output voltage swings are measured between the output and power supply rails. note 8: this parameter is not 100% tested. note 9: thermal resistance varies depending upon the amount of pc board metal attached to the v C pin of the device. q ja is specified for a certain amount of 2oz of copper metal trace connecting to the v C pin as described in the thermal resistance tables in the applications information section. note 10: matching parameters are the difference between the two amplifiers of the lt1810. symbol parameter conditions min typ max units cmrr common mode rejection ratio v cm = v C to v + l 68 86 db cmrr match (channel-to-channel) (note 10) v cm = v C to v + l 62 86 db input common mode range l v C v + v psrr power supply rejection ratio v + = 2.5v to 10v, v C = 0v l 69 83 db psrr match (channel-to-channel) (note 10) v + = 2.5v to 10v, v C = 0v l 63 83 db v ol output voltage swing low (note 7) no load l 23 100 mv i sink = 5ma l 60 170 mv i sink = 25ma l 220 525 mv v oh output voltage swing high (note 7) no load l 75 160 mv i source = 5ma l 130 260 mv i source = 25ma l 375 775 mv i sc short-circuit current l 30 75 ma i s supply current per amplifier l 19 25 ma supply current, shutdown v shdn = 0.3v l 0.65 1.6 ma i shdn shdn pin current v shdn = 0.3v l 420 900 m a output leakage current, shutdown v shdn = 0.3v l 4 m a v l shdn pin input voltage low l 0.3 v v h shdn pin input voltage high l v + C 0.5 v t on turn-on time v shdn = 0.3v to 4.5v, r l = 100 l 80 ns t off turn-off time v shdn = 4.5v to 0.3v, r l = 100 l 50 ns gbw gain-bandwidth product frequency = 2mhz l 80 160 mhz sr slew rate a v = C 1, r l = 1k, v o = 4v, l 110 220 v/ m s measured at v o = 3v fpbw full power bandwidth v out = 8v p-p l 8.5 mhz electrical characteristics
10 lt1809/lt1810 typical perfor a ce characteristics uw supply current vs supply voltage offset voltage vs input common mode input bias current vs common mode voltage total supply voltage (v) 0 supply current (ma) 15 20 25 8 1809 g04 10 5 0 2 4 6 19 3 5 7 10 t a = 125 c t a = 25 c t a = 55 c input bias current vs temperature output saturation voltage vs load current (output low) temperature ( c) ?0 ?5 input bias current ( a) ?3 ? ? ? 5 ? ?0 10 25 85 1809 g07 ?1 1 3 ? ?5 5 40 55 70 v s = 5v, 0v v cm = 5v v cm = 0v load current (ma) 0.01 0.001 output low saturation voltage (v) 0.1 10 110 0.1 100 1809 g08 0.01 1 v s = 5v, 0v t a = 125 c t a = 55 c t a = 25 c output saturation voltage vs load current (output high) load current (ma) 0.01 0.001 output high saturation voltage (v) 0.1 10 110 0.1 100 1809 g09 0.01 1 v s = 5v, 0v t a = 125 c t a = 55 c t a = 25 c v os distribution, v cm = 0v (pnp stage) d v os shift for v cm = 0v to 5v input offset voltage (mv) ? 0 percent of units (%) 10 20 30 40 50 ? ? 0 1 1809 g01 23 v s = 5v, 0v v os distribution, v cm = 5v (npn stage) input offset voltage (mv) ? 0 percent of units (%) 10 20 30 40 50 ? ? 0 1 1809 g02 23 v s = 5v, 0v input offset voltage (mv) ? 0 percent of units (%) 5 10 15 20 25 0.75 0.5 0.25 0 0.25 1809 g03 0.5 0.75 1 v s = 5v, 0v input common mode voltage (v) 0 1.0 1.5 2.0 4 1809 g05 0.5 0 123 5 0.5 1.0 1.5 offset voltage (mv) v s = 5v, 0v typical part t a = 125 c t a = 25 c t a = 55 c common mode voltage (v) ? input bias current ( a) 5 2 1809 g06 ?0 ?0 01 3 ?5 ?0 10 0 ? ?5 456 v s = 5v, 0v t a = 55 c t a = 55 c t a = 25 c t a = 25 c t a = 125 c t a = 125 c
11 lt1809/lt1810 typical perfor a ce characteristics uw shdn pin current vs shdn pin voltage open-loop gain open-loop gain output voltage (v) 0 2.5 input voltage (mv) ?.5 0.5 0.5 0.5 1.0 1.5 2.0 1809 g14 2.5 1.5 2.5 2.0 ?.0 0 1.0 2.0 3.0 r l = 100 v s = 3v, 0v r l = 1k output voltage (v) 0 2.5 input voltage (mv) ?.5 0.5 0.5 1 2 34 1809 g15 1.5 2.5 2.0 ?.0 0 1.0 2.0 5 r l = 100 v s = 5v, 0v r l = 1k offset voltage vs output current warm-up drift vs time (lt1809s8) open-loop gain output voltage (v) ? input voltage (mv) 0.5 1.5 2.5 3 1809 g16 0.5 ?.5 0 1.0 2.0 ?.0 2.0 2.5 ? ? ? ? 12 4 0 5 v s = 5v r l = 1k r l = 100 time after power up (sec) 0 change in offset voltage ( v) 100 120 140 80 100 120 140 160 1809 g18 80 60 0 20 40 60 20 40 180 160 t a = 25 c v s = 5v v s = 5v, 0v v s = 3v, 0v minimum supply voltage total supply voltage (v) 1.5 ?.0 change in offset voltage (mv) 0.8 0.4 0.2 0 1.0 0.4 2.5 3.5 4.0 1809 g10 0.6 0.6 0.8 0.2 2.0 3.0 4.5 5.0 t a = 125 c t a = 55 c v cm = v?+ 0.5v t a = 25 c output short-circuit current vs power supply voltage power supply voltage ( v) 1.5 output short-circuit current (ma) ?0 80 100 120 2.5 3.5 4.0 1809 g11 ?0 40 0 ?0 60 ?00 20 ?0 2.0 3.0 4.5 5.0 t a = 55 c t a = 55 c t a = 125 c t a = 25 c ?inking ?ourcing t a = 25 c t a = 125 c supply current vs shdn pin voltage shdn pin voltage (v) 0 0 supply current (ma) 2 6 8 10 2 4 5 18 1809 g12 4 13 12 14 16 v s = 5v, 0v t a = 55 c t a = 25 c t a = 125 c shdn pin voltage (v) 0 shdn pin current ( a) ?50 ?0 50 4 1809 g13 250 350 200 ?00 0 300 400 450 1 2 3 5 v s = 5v, 0v t a = 125 c t a = 25 c t a = 55 c output current (ma) ?5 offset voltage (mv) ? 5 15 ?0 0 10 60 20 20 60 1809 g17 100 ?0 ?00 40 0 40 80 v s = 5v t a = 125 c t a = 55 c t a = 25 c
12 lt1809/lt1810 typical perfor a ce characteristics uw gain and phase vs frequency gain bandwidth and phase margin vs supply voltage slew rate vs temperature frequency (hz) 0 gain (db) phase (deg) 20 30 50 60 100k 10m 100m 1g 1809 g22 ?0 1m 40 10 ?0 ?0 20 40 80 100 ?0 60 0 ?0 v s = 5v v s = 5v v s = 3v, 0v phase gain v s = 3v, 0v c l = 5pf r l = 1k total supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 190 8 1809 g23 180 170 185 175 165 160 35 45 55 40 50 2 4 6 10 t a = 25 c r l = 1k phase margin gain bandwidth temperature ( c) ?5 slew rate (v/ s) 400 25 1809 g25 250 150 ?5 0 50 100 50 450 350 300 200 75 100 125 a v = 1 r f = r g = 1k r l = 1k rising and falling slew rate v s = 5v v s = 5v, 0v gain bandwidth and phase margin vs temperature temperature ( c) ?5 150 gain bandwidth (mhz) phase margin (deg) 160 180 190 200 0 50 75 1809 g24 170 30 55 40 45 50 35 ?5 25 100 125 v s = 5v v s = 5v v s = 3v, 0v v s = 3v, 0v gain bandwidth phase margin frequency (hz) ? gain (db) 12 15 ? ?2 9 0 6 3 ? 100k 10m 100m 500m 1809 g26 ?5 1m v s = 3v a v = +1 v s = 5v frequency (hz) ? gain (db) 12 15 ? ?2 9 0 6 3 ? 100k 10m 100m 500m 1809 g27 ?5 1m v s = 3v a v = +2 v s = 5v closed-loop gain vs frequency closed-loop gain vs frequency input noise current vs frequency 0.1hz to 10hz output voltage noise input noise voltage vs frequency frequency (khz) 0.1 40 noise voltage (nv/ hz) 50 60 70 80 1 10 100 1809 g19 30 20 10 0 90 100 v s = 5v, 0v npn active v cm = 4.5v pnp active v cm = 2.5v frequency (khz) 0.1 0 current noise (pa/ hz) 12 16 20 1 10 100 1809 g20 8 4 v s = 5v, 0v pnp active v cm = 2.5v npn active v cm = 4.5v time (2 sec/div) output voltage ( v/div) 2 6 10 1809 g21 ? ? 0 4 8 ? ? ?0
13 lt1809/lt1810 typical perfor a ce characteristics uw power supply rejection ratio vs frequency series output resistor vs capacitive load frequency (hz) 1k 10k 40 power supply rejection ratio (db) 50 60 70 80 100k 1m 10m 100m 1809 g31 30 20 10 0 90 100 v s = 5v, 0v t a = 25 c positive supply negative supply capacitive load (pf) 10 0 overshoot (%) 10 20 40 100 1000 1809 g32 30 5 15 35 25 v s = 5v, 0v a v = +1 r s = 10 , r l = r s = 20 , r l = r l = r s = 50 series output resistor vs capacitive load capacitive load (pf) 10 0 overshoot (%) 10 20 30 40 100 1000 1809 g33 50 5 15 25 35 45 v s = 5v, 0v a v = +2 r s = 10 r l = r s = 20 r l = r l = r s = 50 0.01% settling time distortion vs frequency frequency (mhz) 0.3 ?0 distortion (db) ?0 ?0 ?0 11030 1809 g35 ?0 ?0 ?00 ?10 a v = +1 v o = 2v p-p v s = 5v r l = 100 , 2nd r l = 1k, 3rd r l = 1k, 2nd r l = 100 , 3rd input signal generation (2v/div) output settling resolution (2mv/div) v s = 5v 20ns/div 1809 g34 v out = 4v a v = C 1 r l = 500 w t s = 110ns (settling time) distortion vs frequency frequency (mhz) 0.3 ?0 distortion (db) ?0 ?0 ?0 11030 1809 g36 ?0 ?0 ?00 ?10 a v = +1 v o = 2v p-p v s = 5v r l = 100 , 2nd r l = 1k, 3rd r l = 1k, 2nd r l = 100 , 3rd distortion vs frequency frequency (mhz) 0.3 ?0 distortion (db) ?0 ?0 ?0 11030 1809 g37 ?0 ?0 ?00 ?10 a v = +2 v o = 2v p-p v s = 5v r l = 100 , 2nd r l = 100 , 3rd r l = 1k, 3rd r l = 1k, 2nd output impedance vs frequency common mode rejection ratio vs frequency frequency (hz) 100k 1m 10m 100m 500m 0.01 output impedance ( ) 1 600 1809 g28 0.1 10 100 v s = 5v, 0v a v = 10 a v = 1 a v = 2 frequency (hz) 10k 50 common mode rejection ratio (db) 60 70 80 90 100k 1m 10m 100m 500m 1809 g30 40 30 20 10 100 110 v s = 5v, 0v
14 lt1809/lt1810 typical perfor a ce characteristics uw 5v large-signal response 5v large-signal response 5v small-signal response 5v small-signal response shutdown response output overdriven recovery v s = 5v, 0v 100ns/div 1809 g44 a v = +2 v in (1v/div) v out (2v/div) 0v 0v v s = 5v, 0v 100ns/div 1809 g44 a v = +2 r l = 100 w 0v 0v v shdn v out distortion vs frequency maximum undistorted output signal vs frequency frequency (mhz) 0.3 ?0 distortion (db) ?0 ?0 ?0 11030 1809 g38 ?0 ?0 ?00 ?10 a v = +2 v o = 2v p-p v s = 5v r l = 100 , 2nd r l = 100 , 3rd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.1 4.3 output voltage swing (v p-p ) 4.4 4.5 4.6 1 10 100 1809 g39 4.2 4.1 4.0 3.9 v s = 5v a v = ? a v = +2 v s = 5v 10ns/div 1809 g40 a v = +1 r l = 1k v s = 5v 10ns/div 1809 g41 a v = +1 r l = 1k v s = 5v 10ns/div 1809 g42 a v = +1 r l = 1k v s = 5v 10ns/div 1809 g43 a v = +1 r l = 1k
15 lt1809/lt1810 applicatio s i for atio wu uu rail-to-rail characteristics the lt1809/lt1810 have an input and output signal range that includes both negative and positive power supply. figure 1 depicts a simplified schematic of the amplifier. the input stage is comprised of two differential amplifiers, a pnp stage q1/q2 and a npn stage q3/q4 that are active over different ranges of common mode input voltage. the pnp differential pair is active for common mode voltages between the negative supply to approximately 1.5v below the positive supply. as the input voltage moves closer toward the positive supply, the transistor q5 will steer the tail current i 1 to the current mirror q6/q7, activating the npn differential pair and causing the pnp pair to become inactive for the rest of the input common mode range up to the positive supply. a pair of complementary common emitter stages q14/q15 form the output stage, enabling the output to swing from rail-to-rail. the capacitors c1 and c2 form the local feedback loops that lower the output impedance at high frequency. these devices are fabricated on linear technologys proprietary high speed complementary bipolar process. power dissipation the lt1809/lt1810 amplifiers combine high speed with large output current in a small package, so there is a need to ensure that the dies junction temperature does not exceed 150 c. the lt1809 is housed in an so-8 package or a 6-lead sot-23 package and the lt1810 is in an so-8 or 8-lead msop package. all packages have the v C supply pin fused to the lead frame to enhance the thermal conduc- tance when connecting to a ground plane or a large metal trace. metal trace and plated through-holes can be used to spread the heat generated by the device to the backside of the pc board. for example, on a 3/32" fr-4 board with 2oz copper, a total of 660 square millimeters connected to pin 4 of lt1810 in an so-8 package (330 square millime- ters on each side of the pc board) will bring the thermal resistance, q ja , to about 85 c/w. without extra metal trace connected to the v C pin to provide a heat sink, the thermal resistance will be around 105 c/w. more infor- mation on thermal resistance for all packages with various metal areas connecting to the v C pin is provided in tables 1, 2 and 3 for thermal consideration. q4 q6 q3 q7 q10 q1 q13 q15 out q2 q11 q12 q9 q5 v bias i 1 d2 d1 d5 d4 d3 d6 d7 d8 esdd2 esdd1 +in ?n esdd3 esdd4 v + v + q8 r2 r1 r3 r4 r5 q14 1809 f01 i 2 c2 c c v c1 buffer and output bias q17 q16 esdd5 shdn v + r7 100k r6 10k d9 v + v v v v esdd6 bias generation figure 1. lt1809 simplified schematic diagram
16 lt1809/lt1810 applicatio s i for atio wu uu table 1. lt1809 6-lead sot-23 package copper area board area thermal resistance topside (mm 2 ) (mm 2 ) (junction-to-ambient) 270 2500 135 c/w 100 2500 145 c/w 20 2500 160 c/w 0 2500 200 c/w device is mounted on topside. table 2. lt1809/lt1810 so-8 package copper area topside backside board area thermal resistance (mm 2 ) (mm 2 ) (mm 2 ) (junction-to-ambient) 1100 1100 2500 65 c/w 330 330 2500 85 c/w 35 35 2500 95 c/w 35 0 2500 100 c/w 0 0 2500 105 c/w device is mounted on topside. table 3. lt1810 8-lead msop package copper area topside backside board area thermal resistance (mm 2 ) (mm 2 ) (mm 2 ) (junction-to-ambient) 540 540 2500 110 c/w 100 100 2500 120 c/w 100 0 2500 130 c/w 30 0 2500 135 c/w 0 0 2500 140 c/w device is mounted on topside. junction temperature t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? q ja ) the power dissipation in the ic is the function of the supply voltage, output voltage and the load resistance. for a given supply voltage, the worst-case power dissipation p d(max) occurs at the maximum supply current with the output voltage at half of either supply voltage (or the maximum swing is less than 1/2 the supply voltage). p d(max) is given by: p d(max) = (v s ? i s(max) ) + (v s /2) 2 /r l example: an lt1810 in so-8 mounted on a 2500mm 2 area of pc board without any extra heat spreading plane connected to its v C pin has a thermal resistance of 105 c/w, q ja . operating on 5v supplies with both amplifiers simultaneously driving 50 w loads, the worst- case power dissipation is given by: p d(max) = 2 ? (10 ? 25ma) + 2 ? (2.5) 2 /50 = 0.5 + 0.250 = 0.750w the maximum ambient temperature that the part is al- lowed to operate is: t a = t j C (p d(max) ? 105 c/w) = 150 c C (0.750w ? 105 c/w) = 71 c to operate the device at higher ambient temperature, connect more metal area to the v C pin to reduce the thermal resistance of the package as indicated in table 2. input offset voltage the offset voltage will change depending upon which input stage is active and the maximum offset voltage is guaran- teed to be less than 3mv. the change of v os over the entire input common mode range (cmrr) is less than 2.5mv on a single 5v and 3v supply. input bias current the input bias current polarity depends upon a given input common voltage at whichever input stage is operating. when the pnp input stage is active, the input bias currents flow out of the input pins and flow into the input pins when the npn input stage is activated. because the input offset current is less than the input bias current, matching the source resistances at the input pin will reduce total offset error. output the lt1809/lt1810 can deliver a large output current, so the short-circuit current limit is set around 90ma to prevent damage to the device. attention must be paid to keep the junction temperature of the ic below the abso- lute maximum rating of 150 c (refer to the power dissi- pation section) when the output is continuously short circuited. the output of the amplifier has reverse-biased diodes connected to each supply. if the output is forced
17 lt1809/lt1810 applicatio s i for atio wu uu beyond either supply, unlimited current will flow through these diodes. if the current is transient and limited to several hundred milliamps, no damage to the device will occur. overdrive protection when the input voltage exceeds the power supplies, two pairs of crossing diodes, d1 to d4, will prevent the output from reversing polarity. if the input voltage exceeds either power supply by 700mv, diodes d1/d2 or d3/d4 will turn on, keeping the output at the proper polarity. for the phase reversal protection to perform properly, the input current must be limited to less than 5ma. if the amplifier is severely overdriven, an external resistor should be used to limit the overdrive current. the lt1809/lt1810s input stages are also protected against differential input voltages of 1.4v or higher by back-to-back diodes, d5/d8, that prevent the emitter-base breakdown of the input transistors. the current in these diodes should be limited to less than 10ma when they are active. the worst-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity-gain configuration. in addition, the amplifier is protected against esd strikes up to 3kv on all pins by a pair of protection diodes on each pin that are connected to the power supplies as shown in figure 1. capacitive load the lt1809/lt1810 is optimized for high bandwidth and low distortion applications. it can drive a capacitive load about 20pf in a unity-gain configuration and more with higher gain. when driving a larger capacitive load, a resistor of 10 w to 50 w should be connected between the output and the capacitive load to avoid ringing or oscilla- tion. the feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. graphs on capacitive loads indicate the transient response of the amplifier when driving capacitive load with a specified series resistor. feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. for instance, the lt1809 in a noninverting gain of 2, set up with two 1k resistors and a capacitance of 3pf (device plus pc board), will probably ring in transient response. the pole that is formed at 106mhz will reduce phase margin by 34 degrees when the crossover frequency of the amplifier is around 70mhz. a capacitor of 3pf or higher connected across the feedback resistor will eliminate any ringing or oscillation. shdn pin the lt1809 has a shdn pin to reduce the supply current to less than 1.25ma. when the shdn pin is pulled low, it will generate a signal to power down the device. if the pin is left unconnected, an internal pull-up resistor of 10k will keep the part fully operating as shown in figure 1. the output will be high impedance during shutdown, and the turn-on and turn-off time is less than 100ns. because the inputs are protected by a pair of back-to-back diodes, the input signal will feed through to the output during shut- down mode if the amplitude of signal between the inputs is larger than 1.4v.
18 lt1809/lt1810 typical applicatio s u driving a/d converters the lt1809/lt1810 have a 27ns settling time to 0.1% of a 2v step signal and 20 w output impedance at 100mhz making it ideal for driving high speed a/d converters. with the rail-to-rail input and output and low supply voltage operation, the lt1809 is also desirable for single supply applications. as shown in figure 2, the lt1809 drives a 10msps, 12-bit adc, the ltc1420. the lowpass filter, r3 and c1, reduces the noise and distortion products that might come from the input signal. high quality capacitors and resistors, an npo chip capacitor and metal-film sur- face mount resistors, should be used since these compo- nents can add to distortion. the voltage glitch of the converter, due to its sampling nature, is buffered by the lt1809 and the ability of the amplifier to settle it quickly will affect the spurious-free dynamic range of the system. figure 2 to figure 7 depict the lt1809 driving the ltc1420 at different configurations and voltage supplies. the fft responses show better than 90db of sfdr for a 5v supply, and 80db on a 5v single supply for the 1.394mhz signal. + lt1809 ltc1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps ?v ?v r2 1k r1 1k v in 1v p-p c1 470pf ? in 1809 f02 +a in r3 49.9 figure 2. noninverting a/d driver figure 3. 4096 point fft response frequency (mhz) 0 120 amplitude (db) 100 ?0 ?0 ?0 ?0 0 1234 1809 f03 5 v s = 5v a v = +2 f sample = 10msps f in = 1.394mhz sfdr = 90db
19 lt1809/lt1810 typical applicatio s u figure 6. single supply a/d driver + lt1809 ltc1420 pga gain = 2 ref = 4.096v 5v 3 2 4 1 6 7 5v 12 bits 10msps 1k 1k v in 1v p-p on 2.5v dc 470pf 1 f 0.15 f 3 2 1 ? in v cm 1809 f06 +a in 49.9 figure 7. 4096 point fft response figure 4. inverting a/d driver figure 5. 4096 point fft response + lt1809 ltc1420 pga gain = 1 ref = 2.048v 5v 5v 12 bits 10msps ?v ?v 1k 1k v in 2v p-p 470pf ? in 1809 f04 +a in 49.9 frequency (mhz) 0 120 amplitude (db) 100 ?0 ?0 ?0 ?0 0 1234 1809 f05 5 v s = 5v a v = 1 f sample = 10msps f in = 1.394mhz sfdr = 90db frequency (mhz) 0 120 amplitude (db) 100 ?0 ?0 ?0 ?0 0 1234 1809 f07 5 v s = 5v a v = +2 f sample = 10msps f in = 1.394mhz sfdr = 80db
20 lt1809/lt1810 typical applicatio s u single supply video line driver the lt1809 is a wideband rail-to-rail op amp with a large output current that allows it to drive video signals in low supply applications. figure 8 depicts a single supply video line driver with ac coupling to minimize the quiescent power dissipation. resistors r1 and r2 are used to level- shift the input and output to provide the largest signal swing. a gain of 2 is set up with r3 and r4 to restore the signal at v out , which is attenuated by 6db due to the matching of the 75 w line with the back-terminated resistor, r5. the back termination will eliminate any re- flection of the signal that comes from the load. the input termination resistor, r t , is optionalit is used only if matching of the incoming line is necessary. the values of c1, c2 and c3 are selected to minimize the droop of the luminance signal. in some less stringent requirements, the value of capacitors could be reduced. the C 3db band- width of the driver is about 95mhz on 5v supply and the amount of peaking will vary upon the value of capacitor c4. + lt1809 v in 1809 f08 c1 33 f c2 150 f r t 75 r load 75 v out r2 5k r3 1k r4 1k c4 3pf r1 5k 5v 2 3 6 7 4 r5 75 75 coax cable c3 1000 f + + + frequency (mhz) ? voltage gain (db) 4 5 ? ? 3 0 2 1 ? 0.2 10 100 1809 f09 ? 1 v s = 5v figure 8. 5v single supply video line driver figure 9. video line driver frequency response
21 lt1809/lt1810 dimensions in inches (millimeters) unless otherwise noted. u package descriptio 1.50 ?1.75 (.059 ?.069) (note 3) 2.60 ?3.00 (.102 ?.118) .25 ?.50 (.010 ?.020) (6plcs, note 2) l datum ? .09 ?.20 (.004 ?.008) (note 2) a1 s6 sot-23 0401 2.80 ?3.10 (.110 ?.118) (note 3) .95 (.037) ref a a2 1.90 (.074) ref .20 (.008) .90 ?1.45 (.035 ?.057) .00 ?0.15 (.00 ?.006) .90 ?1.30 (.035 ?.051) .35 ?.55 (.014 ?.021) 1.00 max (.039 max) a a1 a2 l .01 ?.10 (.0004 ?.004) .80 ?.90 (.031 ?.035) .30 ?.50 ref (.012 ?.019 ref) pin one id millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 4. dimensions are inclusive of plating 5. dimensions are exclusive of mold flash and metal burr 6. mold flash shall not exceed .254mm 7. package eiaj reference is: sc-74a (eiaj) for original jedec mo-193 for thin sot-23 (original) sot-23 (thinsot) s6 package 6-lead plastic sot-23 (reference ltc dwg # 05-08-1634) (reference ltc dwg # 05-08-1636)
22 lt1809/lt1810 dimensions in inches (millimeters) unless otherwise noted. u package descriptio msop (ms8) 1100 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.043 (1.10) max 0.009 ?0.015 (0.22 ?0.38) 0.005 0.002 (0.13 0.05) 0.034 (0.86) ref 0.0256 (0.65) bsc 12 3 4 0.193 0.006 (4.90 0.15) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660)
23 lt1809/lt1810 dimensions in inches (millimeters) unless otherwise noted. u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610)
24 lt1809/lt1810 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2000 sn180910 180910fs lt/tp 1100 4k ? printed in usa part number description comments lt1395 400mhz current feedback amplifier 800v/ m s slew rate, shutdown lt1632/lt1633 dual/quad 45mhz, 45v/ m s rail-to-rail input and output op amps high dc accuracy, 1.35mv v os(max) , 70ma output current, max supply current 5.2ma per amplifier lt1630/lt1631 dual/quad 30mhz, 10v/ m s rail-to-rail input and output op amps high dc accuracy, 525 m v v os(max) , 70ma output current, max supply current 4.4ma per amplifier lt1806/lt1807 single/dual 325mhz, 140v/ m s rail-to-rail high dc accuracy, 550 m v v os(max) , low noise 3.5nv/ ? hz, input and output op amps low distortion C80dbc at 5mhz figure 10. single 3v supply, 4mhz, 4th order butterworth filter typical applicatio u related parts single 3v supply, 4mhz, 4th order butterworth filter benefiting from a low voltage supply operation, low distortion and rail-to-rail output of lt1809, a low distor- tion filter that is suitable for antialiasing can be built as shown figure 10. on a 3v supply, the filter has a pass- band of 4mhz with 2.5v p-p signal and a stopband that is greater than 70db to frequency of 100mhz. + v s 2 47pf 1/2 lt1810 220pf 665 v in v out 1809 f10 232 232 + 22pf 470pf 562 274 274 1/2 lt1810 frequency (hz) 10k 100k 1m 10m 100m gain (db) 1809 f11 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 v s = 3v, 0v v in = 2.5v p-p figure 11. filter frequency response

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